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FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g ?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 december 2012 FOD8318 2.5 a output current, igbt drive optocoupler with active miller clamp, de saturation detection, and isolated fault sensing features ? high noise immunity characterized by common mode rejection ? 35 kv / s minimum common mode rejection (vcm = 1500 v peak ) ? 2.5 a peak output current driving capability for most 1200 v / 150 a igbt ? optically isolated fault sensing feedback ? active miller clamp to shut off the igbt during high dv/dt without needing a negative supply voltage ? ?soft? igbt turn-off ? built-in igbt protection ? desaturation detection ? under-voltage lock out (uvlo) protection ? wide supply voltage range from 15 v to 30 v ? use of p-channel mosfets at output stage enables output voltage swing close to the supply rail (rail-to-rail output) ? 3.3 v / 5 v, cmos/ttl-compatible inputs ? high speed ? 500 ns max. propagation delay over full operating temperature range ? extended industrial temperat e range, -40c to 100c temperature range ? safety and regulatory approvals ? ul1577, 4,243 v rms for 1 min. ? din en/iec 60747-5-5,1,414 v peak working insulation voltage, 8000 v peak transient isolation voltage ratings ? r ds(on) of 1 ? (typ.) offers lower power dissipation ? user configurable: inverting, non-inverting, auto-reset, auto-shutdown ? 8 mm creepage and clearance distances applications ? industrial inverter ? induction heating ? isolated igbt drive description the FOD8318 is an advanced 2.5 a output current igbt drive optocoupler capable of driving most 1200 v / 150 a igbts. it is ideally suited for fast-switch- ing driving of power igbts and mosfets used in motor control inverter applications and high-performance power systems. it consists of an integrat ed gate drive optocoupler featuring low r ds(on) cmos transistors to drive the igbt from rail to rail and an integrated high- speed isolated feedback for fault sensing. the FOD8318 has an active miller clamp fuction to shut off the igbt during a high dv/dt situation without the need of a nega- tive supply voltage. it offe rs critical protection features necessary for preventing fault conditions that lead to destructive thermal runaway of igbts. it utilizes fairchild?s proprietary optoplanar ? coplanar packaging technology and optimized ic design to achieve high noise immunity, characterized by high common mode rejection and power supply rejection specifications. the device is housed in a compact 16-pin small outline plastic package that meets the 8 mm creepage and clearance requirements.
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 2 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g truth table *v out is always low with ?clamp? being active (gate voltage < 2 v above v ss ). pin definitions v in+ v in? uvlo (v dd2 ? v e ) desat detected? fault v out * xxactivexxlow xxxyeslowlow lowxxxxlow x high x x x low high low not active no high high pin # name description 1v in+ non-inverting gate drive control input 2v in? inverting gate drive control input 3v dd1 positive input supply voltage (3 v to 5.5 v) 4 gnd1 input ground 5 reset fault reset input 6fault fault output 7v led1+ led 1 anode (must be left unconnected) 8v led1- led 1 cathode (must be connected to ground) 9v ss output supply voltage (negative) 10 v clamp active miller clamp supply voltage 11 v o gate drive output voltage 12 v s source of pull-up pmos transistor 13 v dd2 positive output supply voltage 14 desat desaturation voltage input 15 v led2+ led 2 anode (must be left unconnected) 16 v e output supply voltage / igbt emitter 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 3 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g block diagram driver v dd1 v dd2 v led1+ 3 13 7 v s 12 v o 11 v ss 9 desat 14 v e 16 v in+ 1 v in? 2 reset fault uvlo desat led1 led2 fault sense optocoupler gate drive optocoupler shield shield 5 fault input ic output ic v led2+ 6 15 gnd1 4 v led1? 8 v ss v clamp 10 miller clamp
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 4 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g safety and insulation ratings as per din en/iec 60747-5-5. this optocoupler is suitable fo r ?safe electrical insulation? only within the safety limit data. compliance with the safety ratings shall be ensured by means of protective circuits. symbol parameter min. typ. max. unit installation classifications per din vde 0110/1.89 table 1 for rated mains voltage < 150 vrms i?iv for rated mains voltage < 300 vrms i?iv for rated mains voltage < 450 vrms i?iv for rated mains voltage < 600 vrms i?iv for rated mains voltage < 1000 vrms i?iii climatic classification 40/100/21 pollution degree (din vde 0110/1.89) 2 cti comparative tracking index 175 v pr input to output test voltage, method b, v iorm x 1.875 = v pr , 100 % production test with t m = 1 s, partial discharge < 5 pc 2,651 v peak input to output test voltage, method a, v iorm x 1.5 = v pr , type and sample test with t m = 60 s, partial discharge < 5 pc 2,121 v peak v iorm maximum working insulati on voltage 1,414 v peak v iotm highest allowable over voltage 8,000 v peak external creepage 8 mm external clearance 8 mm insulation thickness 0.5 mm safety limit values ? maximum values allowed in the event of a failure t case case temperature 150 c p s,input input power 100 mw p s,output output power 600 mw r io insulation resistance at t s , v io = 500 v 10 9 ?
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 5 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g absolute maximum ratings (t a = 25 oc unless otherwise specified) stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the reco mmended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. notes: 1. maximum pulse width = 10 s, maximum duty cycle = 0.2 %. 2. this negative output supply voltage is optional. it?s only needed when negative gate drive is implemented. a schottky diode is recommended to be connected between v e and v ss to protect against a revers e voltage greater than 0.5 v. refer to application information, ?6. active miller clamp function? on page 25 . 3. no derating required ac ross temperature range. 4. derate linearly above 64 c, free air temperature at a rate of 10.2 mw/c 5. functional operation under t hese conditions is not implie d. permanent damage may occur if the device is subjected to conditions outside these ratings. symbol parameter value units t stg storage temperature -40 to +125 oc t opr operating temperature -40 to +100 oc t j junction temperature -40 to +125 oc t sol lead wave solder temperature (no solder immersion) refer to page 28 for reflow temperature profile. 260 for 10 s oc i fault fault output current 15 ma i o(peak) peak output current (1) 3a v e ? v ss negative output supply voltage (2) 0 to 15 v v dd2 ? v e positive output supply voltage -0.5 to 35 ? (v e ? v ss )v v o(peak) gate drive output voltage -0.5 to 35 v v dd2 ? v ss output supply voltage -0.5 to 35 v v dd1 positive input supply voltage -0.5 to 6 v v in+ , v in- and v reset input voltages -0.5 to v dd1 v v fault fault pin voltage -0.5 to v dd1 v v s source of pull-up pmos transistor voltage v ss + 6.5 to v dd2 v v desat desat voltage v e to v e + 11 v i clamp peaking clamping sinking current 1.7 a v clamp miller clamping voltage -0.5 to v dd2 v pd i input power dissipation (3)(5) 100 mw pd o output power dissipation (4)(5) 600 mw
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 6 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g recommended oper ating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal perfor mance to the datasheet specif ications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. note: 6. during power up or down, it is important to ensure t hat vin+ remains low until bot h the input and output supply voltages reach the proper recommended operating voltage to avoid any momentary instab ility at the output state. refer to ?time to good power? section on page 25. isolation characteristics apply over all recommended conditions, typical value is measured at t a = 25 oc notes: 7. device is considered a two terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together. 8. 4,243 v rms for 1-minute duration is equivalent to 5,091 v rms for 1-second duration. 9. the input-output isolation voltage is a dielectric volt age rating as per ul1577. it should not be regarded as an input-output continuous voltag e rating. for the continuous working voltage rating, refer to the equipment level safety specification or din en/iec 60747-5-5 safety and insulation ratings table on page 4 . electrical characteristics apply over all recommended conditions; typical value is measured at v dd1 = 5 v, v dd2 ? v ss = 30 v, v e ? v ss = 0 v, t a = 25 c unless otherwise specified. symbol parameter min. max. unit t a ambient operating temperature -40 +100 oc v dd1 input supply voltage (6) 35.5v v dd2 ? v ss total output supply voltage 15 30 v v e ? v ss negative output supply voltage 0 15 v v dd2 ? v e positive output supply voltage (6) 15 30 ? (v e ? v ss )v v s source of pull-up pmos transistor voltage v ss + 7.5 v dd2 v symbol parameter conditions min. typ. max. units v iso input-output isolation voltage t a = 25 oc, r.h.< 50 %, t = 1.0 min, i i-o e 10 a, 50 hz (7)(8)(9) 4,243 v rms r iso isolation resistance v i-o = 500 v (7) 10 11 ? c iso isolation capacitance v i-o = 0 v, freq = 1.0 mhz (7) 1pf symbol parameter conditions min. typ. max. units figure v in+l , v in-l , v resetl logic low input voltages 0.8 v v in+h , v in-h , v reseth logic high input voltages 2.0 v i in+l , i in-l , i resetl logic low input currents v in = 0.4 v -0.5 -0.001 ma i faultl fault logic low output current v fault = 0.4 v 5.0 12.0 ma 1, 35 i faulth fault logic high output current v fault = v dd1 -40 0.002 a 35 i oh high level output current v o = v dd2 ? 3 v -1 -3 a 2, 7, 36 v o = v dd2 ? 6 v (10) -2.5 a
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 7 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g notes: 10. maximum pulse width = 10 s, maximum duty cycle = 0.2 %. 11. maximum pulse width = 4.99 ms , maximum duty cycle = 99.8 %. 12. v oh is measured with the dc load curren t in this testing (maximum pulse width = 1 ms, maximum duty cycle = 20 %). when driving capacitive loads, v oh approaches v dd as i oh approaches zero units. 13. positive output supply voltage (v dd2 ? v e ) should be at least 15 v. this ensures adequate margin in excess of the maximum under-voltage lockout threshold v uvlo+ of 13.5 v. 14. when v dd2 ? v e > v uvlo and output state v o of the FOD8318 is allowed to go high, the desat detection feature is active and provides the primary source of igbt pr otection. uvlo is needed to ensure desat detection is functional. 15. the blanking time, t blank , is adjustable by an external capacitor (c blank ) where t blank = c blank * (v desat / i chg ). i ol low level output current v o = v ss + 3 v 1 3 a 3, 37 v o = v ss + 6 v (11) 2.5 a i olf low level output current during fault condition v o ? v ss = 14 v 90 185 230 ma 4, 41 v oh high level output voltage i o = ?100 ma (12)(13)(14) v s ? 1.0 v v s ? 0.5 v v 5, 7, 38 v ol low level output voltage i o = 100 ma 0.1 0.5 v 6, 8, 38 i dd1h high level supply current v in+ = v dd1 = 5.5 v, v in? = 0 v 14 17 ma 9, 39 i dd1l low level supply current v in+ = v in- = 0 v, v dd1 = 5.5 v 23ma i dd2h high level output supply current v o = open (14) 1 3 ma 10, 11, 40 i dd2l low level output supply current v o = open 0.8 2.8 ma i sh high level source current i o = 0 ma 0.65 1.5 ma 40 i sl low level source current i o = 0 ma 0.6 1.4 ma 40 i el v e low level supply current -0.5 -0.2 ma 13, 40 i eh v e high level supply current -0.5 -0.25 ma i chg blanking capacitor charge current v desat = 2 v (14)(15) -0.13 -0.25 -0.37 ma 12, 41 i dschg blanking capacitor discharge current v desat = 7 v 10 36 ma 41 v uvlo+ under-voltage lockout threshold (14) v o > 5 v at 25 c 11.5 13.5 v 15, 29, 42 v uvlo- v o < 5 v at 25 c 9 10 v uvlo hys under-voltage lockout threshold hysteresis at 25 c 0.4 1.5 v v desat desat threshold (14) v dd2 ? v e > v uvlo- , v o < 5 v 6 7 9 v 16, 41 v clamp_ thres clamping threshold voltage 2.2 v 33, 52 i clampl clamp low level sinking current v o = v ss + 2.5 v 0.35 1.2 a 32, 51 symbol parameter conditions min. typ. max. units figure electrical characteristics (continued) apply over all recommended conditions; typical value is measured at v dd1 = 5 v, v dd2 ? v ss = 30 v, v e ? v ss = 0 v, t a = 25 c unless otherwise specified.
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 8 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g switching characteristics apply over all recommended conditions; typical value is measured at v dd1 = 5 v, v dd2 ? v ss = 30 v, v e ? v ss = 0 v, t a = 25 c unless otherwise specified. notes: 16. this load condition approximates the gate load of a 1200 v / 150 a igbt. 17. t phl propagation delay is measured from the 50 % level on the falling edge of the input pulse (v in+ , v in- ) to the 50 % level of the falling edge of the v o signal. refer to figure 53. 18. t phl propagation delay is measured from the 50 % level on the rising edge of the input pulse (v in+ , v in- ) to the 50 % level of the rising edge of the v o signal. refer to figure 53. 19. pwd is defined as | t phl ? t plh | for any given device. 20. the difference between t phl and t plh between any two FOD8318 parts under sa me operating conditions, with equal loads. 21. this is the amount of time the d esat threshold must be exceeded before v o begins to go low. this is supply voltage dependent. refer to figure 54. symbol parameter conditions min. typ. max. units figure t phl propagation delay time to logic low output (17) rg = 10 ?, cg = 10 nf, f = 10 khz, duty cycle = 50 % (16) 300 500 ns 17, 18, 19, 20, 21, 22, 43, 51 t plh propagation delay time to logic high output (18) 250 500 ns pwd pulse width distortion, | t phl ? t plh | (19) 50 300 ns pdd skew propagation delay difference between any two parts or channels, ( t phl ? t plh ) (20) ?350 350 ns t r output rise time (10 % ? 90 %) 34 ns 43, 53 t f output fall time (90 % ? 10 %) 34 ns t desat(90 %) desat sense to 90 % v o delay (21) rg = 10 ?, cg = 10 nf, v dd2 ? v ss = 30 v 850 ns 23, 44 t desat(10 %) desat sense to 10 % v o delay (21) 2 3 s 24, 26, 27, 44 t desat(fault ) desat sense to low level fault signal delay (22) 1.8 5 s 25, 44, 54 t desat(low) desat sense to desat low propagation delay (23) 850 ns 44 t reset (fault ) reset to high level fault signal delay (24) 3 6 20 s 28, 45, 54 pw reset reset signal pulse width 1.2 s t uvlo on uvlo turn on delay (25) v dd2 = 20 v in 1.0ms ramp 4 s 29, 46 t uvlo off uvlo turn off delay (26) 3s t gp time to good power (27) v dd2 = 0 to 30 v in 10 s ramp 30 s 30, 31, 46 | cm h | common mode transient immunity at output high t a = 25 oc, v dd1 = 5 v, v dd2 = 25 v, v ss = ground, v cm = 1500 v peak (28) 35 50 kv/s 48, 49 | cm l | common mode transient immunity at output low t a = 25 oc, v dd1 = 5 v, v dd2 = 25 v, v ss = ground, v cm = 1500 v peak (29) 35 50 kv/s 47, 50
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 9 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g 22. this is the amount of time from when th e desat threshold is exceeded, until the fault output goes low. refer to figure 54. 23. this is the amount of time the d esat threshold must be exceeded before v o begins to go low and the fault output to go low. refer to figure 54. 24. this is the amount of time from when reset is asserted low, until fault output goes high. refer to figure 54. 25. t uvlo on uvlo turn-on delay is measured from v uvlo+ threshold voltage of the output supply voltage (v dd2 ) to the 5 v level of the rising edge of the v o signal. 26. t uvlo off uvlo turn-off delay is measured from v uvlo? threshold voltage of the output supply voltage (v dd2 ) to the 5 v level of the falling edge of the v o signal. 27. t gp time to good power is measured from 13.5 v leve l of the rising edge of the output supply voltage (v dd2 ) to the 5 v level of the rising edge of the v o signal. 28. common mode transient immunity at output high state is t he maximum tolerable negative dvcm / dt on the trailing edge of the common mode pulse, v cm , to assure that the output remains in high state (i.e., v o > 15 v or fault > 2 v). 29.common mode transient immunity at output lo w state is the maximum positive tolerable dvcm / dt on the leading edge of the common mode pulse, v cm , to assure that the output remains in a low state (i.e., v o < 1.0 v or fault < 0.8 v).
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 10 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g typical performan ce characteristics i oh ? output high current (a) figure 2. output high current (i oh ) vs. temperature figure 4. low level output current (i olf ) vs. output voltage (v o ) figure 5. output high voltage (v oh ?v dd2 ) vs. temperature figure 3. output low current (i ol ) vs. temperature 7 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v o = v dd2 ? 6 v v o = v dd2 ? 3 v i ol ? output low current (a) 7 6 5 4 3 2 1 0 (v oh ?v dd2 ) ? high output voltage drop (v) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v o = v ss + 6 v v o = v ss + 3 v v dd2 ? v ss = 30 v v dd1 = 5 v i olf ? low level output current during fault conditions (ma) 225 200 175 150 125 100 75 50 25 0 5 10 15 20 25 30 v o ? output voltage (v) -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v v dd1 = 5 v v dd2 ? v ss = 30 v v dd1 = 5 v i faultl ? fault current (ma) figure 1. fault logic low output current (i faultl ) vs. fault logic low output voltage (v faultl ) 50 40 30 20 10 0 01234 5 v faultl ? fault voltage (v) v dd1 = 5 v vin+ = 5 v i led2+ = 10 ma t a = 25 c t a = -40 c i o = -650 a i o = -100 ma t a = 25 c t a = 100 c v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 5 v v ol ? output low voltage (v) 0.25 0.20 0.15 0.10 0.05 0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 0 v i o = 100 ma figure 6. output low voltage (v ol ) vs. temperature
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 11 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g typical performan ce characteristics (continued) figure 7. output high voltage (v oh ) vs. output high current (i oh ) figure 9. supply current (i dd1 ) vs. temperature figure 10. output supply current (i dd2 ) vs. temperature figure 12. blanking capacitor charging current (i chg ) vs. temperature figure 11. output supply current (i dd2 ) vs. output supply voltage (v dd2 ) figure 8. output low voltage (v ol ) vs. output low current (i ol ) v oh ? output high voltage (v) 30 29 28 27 26 25 0 0.5 1.0 1.5 2.0 2.5 i oh ? output high current (a) v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 5 v i dd1 ? supply current (ma) 20 15 10 5 0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd1 = 5.5 v v in+ = 5 v (i dd1h ) or 0 v (i dd1l ) i dd1h i dd1l t a = -40 c 25 c 100 c i dd2 ? output supply current (ma) 1.2 1.0 0.8 0.6 0.4 15 20 25 30 v dd2 ? output supply voltage (v) v ol ? output low voltage (v) 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 2.5 i ol ? output low current (a) v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 0 v -40 c 25 c t a = 100 c i dd2 ? output supply current (ma) 1.4 1.2 1.0 0.8 0.6 0.4 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 5 v (i dd2h ) or 0 v (i dd2l ) i dd2h i dd2l i dd2h i dd2l v dd1 = 5 v v in+ = 5 v (i dd2h ) or 0 v (i dd2l ) i chg ? blanking capacitor charging current (ma) -0.15 -0.20 -0.25 -0.30 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 5 v v desat = 0 v to 6 v
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 12 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g typical performan ce characteristics (continued) i s ? source current (ma) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 i o ? output current (ma) v desat ? desat threshold (v) 8.0 7.5 7.0 6.5 6.0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 5 v v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 5 v -40 c 25 c 100 c t p ? propagation delay ( s) 0.5 0.4 0.3 0.2 0.1 figure 17. propagation delay (t p ) vs. temperature -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v v dd1 = 5 v f = 10 khz 50 % duty cycle r l = 10 , c l = 10 nf t plh t phl t p ? propagation delay ( s) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 figure 18. propagation delay (t p ) vs. supply voltage (v dd2 ) 15 20 25 30 v dd2 ? supply voltage (v) v dd1 = 5 v f = 10 khz 50 % duty cycle r l = 10 , c l = 10 nf t plh t phl figure 13. supply current (i e ) vs. temperature figure 16. desat threshold (v desat ) vs. temperature figure 14. source current (i s ) vs. output current (i o ) i e ? supply current (ma) -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -0.40 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 5 v (i eh ) / 0 v (i el ) i el i eh figure 15. under-voltage lockout threshold (v uvlo ) vs. temperature v uvlo ? under voltage lockout threshold (v) 15 10 5 0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd1 = 5 v v in+ = 5 v v uvlo? v uvlo+
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 13 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g typical performan ce characteristics (continued) t p ? propagation delay ( s) t desat(90 %) ? desat sense to 90 % v o delay ( s) 0.40 0.35 0.30 0.25 0.20 figure 21. propagation delay (t p ) vs. load capacitance (c l ) 0 20406080100 c l ? load capacitance (nf) v dd2 ? v ss = 30 v v dd1 = 5 v f = 10 khz 50 % duty cycle r l = 10 t plh t phl t p ? propagation delay ( s) 0.40 0.35 0.30 0.25 0.20 figure 22. propagation delay (t p ) vs. load resistance (r l ) 0 1020304050 r l ? load resistance ( ) v dd2 ? v ss = 30 v v dd1 = 5 v f = 10 khz 50 % duty cycle c l = 10 nf t plh t phl t plh ? propagation delay ( s) 0.45 0.40 0.35 0.30 0.25 figure 19. propagation delay to logic high output (t plh ) vs. temperature figure 20. propagation delay to logic low output (t phl ) vs. temperature -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v f = 10 khz 50 % duty cycle r l = 10 , c l = 10 nf v dd1 = 4.5 v v dd1 = 5.0 v v dd1 = 5.5 v t phl ? propagation delay ( s) 0.35 0.30 0.25 0.20 0.15 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v f = 10 khz 50 % duty cycle r l = 10 , c l = 10 nf v dd1 = 4.5 v v dd1 = 5.0 v v dd1 = 5.5 v 1.2 1.1 1.0 0.9 0.8 figure 23. desat sense to 90 % v o (t desat(90 %) ) vs. temperature figure 24. desat sense to 10 % v o delay (t desat(10 %) ) vs. temperature -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 5 v r l = 10 , c l = 10 nf t desat(10 %) ? desat sense to 10 % v o delay ( s) 3.0 2.5 2.0 1.5 1.0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 15 or 30 v v dd1 = 5 v v in+ = 5 v r l = 10 , c l = 10 nf v dd2 ? v ss = 30 v v dd2 ? v ss = 15 v
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 14 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g typical performan ce characteristics (continued) 0.0030 0.0250 0.0020 0.0015 0.0010 10 20 30 40 50 r l ? load resistance ( ) v dd2 ? v ss = 15 v or 30 v v dd1 = 5 v v in+ = 5 v c l = 10 nf t desat(10 %) ? desat sense to 10 % v o delay ( s) v dd2 ? v ss = 30 v v dd2 ? v ss = 15 v t reset(fault) ? reset to high level fault signal delay ( s) 10 9 8 7 6 5 4 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v v in+ = 5 v r l = 10 , c l = 10 nf v dd1 = 5.5 v v dd1 = 5.0 v v dd1 = 4.5 v figure 25. desat sense to low fault signal delay (t desat(fault) ) vs. temperature figure 26. desat sense to 10 % v o delay (t desat(10 %) ) vs. load capacitance (c l ) figure 27. desat sense to 10 % v o delay (t desat(10 %) ) vs. load resistance (r l ) figure 28. reset to high level fault signal delay (t reset(fault) ) vs. temperature t desat(fault) ? desat sense to low fault signal delay ( s) 2.6 2.4 2.2 2.0 1.8 1.6 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 5 v r l = 10 , c l = 10 nf v e ? v ss = 0 v v e ? v ss = 15 v 0.008 0.006 0.004 0.002 0 0 5 10 15 20 25 30 c l ? load capacitance (nf) v dd2 ? v ss = 15 v or 30 v v dd1 = 5 v v in+ = 5 v r l = 10 t desat(10 %) ? desat sense to 10% v o v dd2 ? v ss = 30 v v dd2 ? v ss = 15 v figure 29. under voltage lockout threshold delay (t uvlo ) vs. temperature t uvlo ? under voltage lockout threshold delay ( s) 10 8 6 4 2 0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 = 20 v v dd1 = 5 v v in+ = 5 v f = 50 hz, 50 % duty cycle t r = 1 ms t uvlo on t uvlo off figure 30. time to good power (t gp ) vs. supply voltage (v dd2 ) t gp ? time to good power ( s) 100 80 60 40 20 0 15 25 20 30 v dd2 ? supply voltage (v) v dd1 = 5 v v in+ = 5 v f = 50hz, 50 % duty cycle
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 15 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g typical performan ce characteristics (continued) figure 31. time to good power (t gp ) vs. temperature t gp ? time to good power ( s) 120 100 80 60 40 20 0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 = 15 v to 30 v v dd1 = 5 v v in+ = 5 v f = 50 hz 50 % duty cycle figure 32. clamp low level sinking current (i clampl ) vs. temperature i clamp ? clamp low level sinking current (a) 3 2.5 2.0 1.5 1.0 0.5 0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 5 v v clamp = 2.5 v figure 33. clamping threshold voltage (v clamp ) vs. temperature v clamp ? clamp pin threshold voltage (v) 2.6 2.4 2.2 2.0 1.8 1.6 1.4 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 0 v figure 34. clamp low level sinking current (i clampl ) vs. clamp voltage (v clamp ) i clamp ? clamp low level sinking current (a) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 v clamp ? clamp voltage (v) v dd2 ? v ss = 30 v v dd1 = 5 v v in+ = 0 v
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 16 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g test circuits figure 35. fault output current (i fault l ) and (i fault h ) test circuit figure 36. high level output current (i oh ) test circuit figure 37. low level output current (i ol ) test circuit 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 0.1 f 0.1 f 10 ma 5 v + C C + i fault v fault v fault = 0.4 v for i faultl v fault = 5.0 v for i faulth switch a closed for i faultl switch a opened for i faulth *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). a 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 pulse gen pw = 10 s period = 5 ms 5 v C + 0.1 f 0.1 f 47 f 47 f 0.1 f 0.1 f + C 30 v + C v e + C 3 k v o + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). pulse gen pw = 4.99 ms period = 5 ms 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 5 v C + 0.1 f 0.1 f 47 f 0.1 f + C 30 v + C v e + C 3 k 47 f 0.1 f v o + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1).
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 17 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g test circuits (continued) figure 38. high level (v oh ) and low level (v ol ) output voltage test circuit figure 39. high level (i dd1h ) and low level (i dd1l ) supply current test circuit figure 40. high level (i dd2h ), low level (i dd2l ) output supply current, high level (i sh ), low level (i sl ) source current, v e high level (i eh ), and v e low level (i el ) supply curren t test circuit 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 v e v o switch a for v oh test switch b for v ol test 0.1 f a a b b 0.1 f 0.1 f 100 ma pulsed 100 ma pulsed 3 k 5 v 30 v + C + C + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). switch a for i dd1h test switch b for i dd1l test 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 i dd1 0.1 f 5 v + C a b *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). switch a for i dd2h, i sh and i eh test switch b for i dd2l, i sl and i el test i dd2 i s i e 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 v e v o 0.1 f 0.1 f 0.1 f 5 v 30 v + C + C + C a b *pin 8 (v led1- ) is internally connected to pin 4 (gnd1).
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 18 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g test circuits (continued) figure 41. low level output current during fault conditions (i olf ), blanking capacitor charge current (i chg ), blanking capacitor discharging current (i dschg ), and desat threshold (v desat ) test circuit figure 42. under-voltage lockout threshold (v uvlo ) test circuit figure 43. propagation delay (t plh , t phl ), pulse width distortion (pwd), rise time (t r ), and fall time (t f ) test circuit 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 v e v desat v o i chg/dschg i olf 0.1 f rl 0.1 f 10 nf 0.1 f 3 k 5 v 30 v + C + C + C + C v rl *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 v o 0.1 f 0.1 f 5 v dc sweep 0 to 15 v (100 steps) parameter analyzer + C + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 v e v o 0.1 f 0.1 f 10 nf 0.1 f 3 k rl 5 v 30 v + C + C + C f = 10 khz dc = 50 % + C v cl *pin 8 (v led1- ) is internally connected to pin 4 (gnd1).
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 19 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g test circuits (continued) figure 44. desat sense (t desat(90 %) , t desat(10 %) ), desat fault (t desat(fault ) ), and (t desat(low) ) test circuit figure 45. reset delay (t reset (fault ) ) test circuit figure 46. under-voltage lockout delay (t uvlo ) and time to good power (t gp ) test circuit 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 v e v o 0.1 f 0.1 f 100 pf 10 nf 0.1 f 3 k rl 5 v 30 v + C + C + C low to high + C v fault *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 v e v o 0.1 f 0.1 f 10 nf 0.1 f 3 k rl 5 v 30 v + C + C + C v fault strobe 8 v + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 v e v o v dd2 ** **1.0 ms ramp for t uvlo 10 s ramp for t gp 0.1 f 0.1 f 0.1 f 3 k 5 v + C + C + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1).
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 20 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g test circuits (continued) figure 47. common mode low (cm l ) test circuit at led1 off figure 48. common mode high (cm h ) test circuit at led1 on 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 scope v cm floating gnd 0.1 f 0.1 f 25 v 10 nf 1 k 10 5 v 300 pf *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 scope v cm floating gnd 0.1 f 0.1 f 25 v 10 nf 1 k 10 5 v 300 pf *pin 8 (v led1- ) is internally connected to pin 4 (gnd1).
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 21 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g test circuits (continued) figure 49. common mode high (cm h ) test circuit at led2 off figure 50. common mode low (cm l ) test circuit at led2 on 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 v cm floating gnd 0.1 f 0.1 f 25 v 10 nf 1 k 10 5 v 300 pf scope *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 v cm floating gnd 0.1 f 0.1 f 25 v 10 nf 1 k 10 750 5 v 300 pf scope 9 v + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1).
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 22 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g test circuits (continued) figure 51. clamp low level sinking current (i clampl ) figure 52. clamp pin threshold voltage (v clamp ) 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 0 v 0.1 f 0.1 f 0.1 f 3 k 5 v 30 v + C + C + C + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). i clampl pulsed v clamp 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss 16 15 14 13 12 11 10 9 FOD8318 0 v 0.1 f 0.1 f 3 k 50 5 v 30 v + C + C + C + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). initially set s1 to a before connecting 3 v to clamp pin. then switch to b before sweeping down to get the v clamp_thres , clamping threshold voltage. sweep from 3 v to v clamp_thres a s1 b 0.1 f
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 23 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g timing diagrams figure 53. propagation delay (t plh , t phl ), rise time (t r ), and fall time (t f ) timing diagram figure 54. definitions for fault reset input (reset ), desaturation voltage input (desat), output voltage (v o ), and fault output (fault ) timing waveforms v in+ v in? v o 2.5 v 0 v t r 90 % 50 % 10 % 2.5 v t plh t phl t f reset v desat v o t desat (low) fault t desat (90 %) t desat (10 %) t desat (fault) t reset (fault) 50 % 90 % 7 v 10 % 50 % 50 % (0.5 x v dd1 )
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 24 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g application information figure 55. recommended application circuit functional description the functional behavioral of FOD8318 is illustrated by the detailed internal schematic shown in figure 56. this explains the interaction and sequence of internal and external signals, together with the timing diagrams. 1. non-inverting and inverting inputs there are two cmos/ttl-compatible inputs, v in+ and v in- , to control the igbt in non-inverting and inverting configurations, respectively. when v in- is set to low state, v in+ controls the driver output, v o , in non-inverting configuration. when v in+ is set to high state, v in- con- trols the driver output in inverting configuration. the relationship between the inputs and output are illustrated in the figure 57. during normal operation, when no fault is detected, the fault output, which is an op en-drain configuration, is latched to high state. this allows the gate driver to be controlled by the input logic signal. when a fault is detected, the fault output is latched to low state. this condition re mains until the input logic is pulled to low and the reset pin is also pulled low for a period longer than pw reset . 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 + +? ? + ? v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v clamp v ss FOD8318 micro controller 3 k 330 pf + C 0.1 f 5 v 3-phase output + C 1 f 10 f 100 pf 1 k 1 f v dd2 = 15 v d desat c blank rg v f v ce v ce q1 q2 *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). v clamp 10 + ? 2 v 25x v dd2 13 v s 12 v o 11 50x 1x v ss 9 desat + ? ? + 14 250 a 12 v v e 16 v in+ 1 15 7 v dd1 3 v in? 2 v led1? v led+ v led2+ 8 gnd1 5 s pulse generator gate drive optocoupler fault sense optocoupler uvlo comparator delay q rs 4 reset 5 fault 6 v desat figure 56. detailed internal schematic
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 25 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g 2. gate driver output a pair of pmos and nmos comprise the output driver stage, which facilitates clos e to rail-to-rail output swing. this feature allows a tight control of gate voltage during on-state and short-circuit condi tion. the output driver is typically to sink 2 a and sour ce 2 a at room temperature. due to the low r ds(on) of the mosfets, the power dis- sipation is reduced as compared to those bipolar-type driver output stages. the absolute maximum rating of the output peak current, i o(peak) , is 3 a; therefore the careful selection of the gate resistor, rg, is required to limit the short-circuit current of the igbt. as shown in figure 56, gate driver output is influenced by signals from the photodetector circuitry, the uvlo comparator, and the desat signals. under no-fault condition, normal operation resumes while the supply voltage is above the uvlo th reshold, the output of the photodetector drives the mosf ets of the output stage. the logic circuitry of the output stage ensures that the push-pull devices are never ?on? simultaneously. when the output of the photodetec tor is high, the output, v o , is pulled to high state by turning on the pmos. when the output of the photodetector is low, v o is pulled to low state by turning on the nmos. when v dd2 supply goes below v uvlo , which is the des- ignated uvlo threshold at the comparator, v o is pulled down to low state regardless of photodetector output. when desaturation is detected, v o turns off slowly as it is pulled low by the nmos 1x device. the input to the fault sense circuitry is latched to high state and turns on the led. when v o goes below 2 v, the nmos 50x device turns on again, clamping the igbt gate firmly to v ss . the fault sense signal remains latched in the high state until the led of the gate driver circuitry turns off. 3. desaturation protection, fault output desaturation detection protection ensures the protection of the igbt at short-circui t by monitoring the collector- emitter voltage of the igbt in the half bridge. when the desat voltage goes up and reaches above the thresh- old voltage, a short-circuit condition is detected and the driver output stage executes a ?soft? igbt turn-off and is eventually driven low, as i llustrated in figure 58. the fault open-drain output is triggered active low to report a desaturation error. it is only cleared by activating active low by the external controller to the reset input with the input logic is pulled to low. the desat fault detector shoul d be disabled for a short period (blanking time) before the igbt turns on to allow the collector voltage to fall below desat threshold. this blanking period protects aga inst false trigger of the desat while the igbt is turning on. the blanking time is controlled by the internal desat charge current, the desat voltage threshold, and the external desat capacito r (capacitor between desat and v e pin). the nominal blanking time can be calcu- lated using external capacitance (c blank ), fault threshold voltage (v desat ), and desat charge current (i chg ) as: t blank = c blank x v desat / i chg with a recommended 100 pf desat capacitor, the nominal blanking time is: 100 pf x 7 v / 250 a = 2.8 s 4. ?soft? turn-off the soft turn-off feat ure ensures the safe turn off of the igbt under fault conditions. this reduces the voltage spike on the collector of the igbt. without this, the igbt would see a heavy spike on the collector and result in permanent damage to the device. 5. under-voltage lockout under-voltage detection pr events the application of insufficient gate voltage to the igbt. this could be dan- gerous, as it would drive the igbt out of saturation and into the linear operation where the losses are very high and quickly overheated. this feature ensures the proper operating of the igbts. the output voltage, v o , remains low regardless of the inputs as long as the supply volt- age, v dd2 ? v e , is less than v uvlo+ . when the supply voltage falls below v uvlo- , v o goes low, as illustrated in figure 59. 6. active miller clamp function an active miller clamp feature allows the sinking of the miller current to the ground or emitter of the igbt during a high-dv/dt situation. instead of driving the igbt gate to a negative supply voltage to increase the safety margin, the device has a dedicated v clamp pin to control the miller current. during turn-off, the gate voltage of the igbt is monitored and the v clamp output is activated when the gate voltage goes below 2 v (relative to v ss ). the miller clamp nmos transistor is then turned on and provides a low resistive path for the miller current. this helps prevent a self-turn-on due to the parasitic miller capacitor in power switches. the clamp voltage is v ol + 2.5 v maximum for a mille r current up to 1200 ma. in this way, the v clamp function does not affect the turn- off characteristic. it helps to clamp the gate to the low level throughout the turn-off time. during turn-on, where the input of the driver is activated, the v clamp function is disabled or opened. 7. time to good power at initial power up, the led is off and the output of the gate driver should be in the low state. sometimes race conditions exist that causes the output to follow the v e (assuming v dd2 and v e are connected externally), until all of the circuits in the output ic have stabilized. this condition can result in outp ut transitions or transients that are coupled to the driv en igbt. these glitches can cause the high-side and low-side igbts to conduct shoot-through current that may result in destructive damage to the power semiconductor devices. fairchild has introduced a initial turn -on delay, generally called ?time-to-good power?. this delay, typically 30 s, is only
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 26 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g present during the initial po wer-up of the device. once powered, the ?time-to-good power? delay is determined by the delay of the uvlo ci rcuitry. if the led is ?on? during the initial turn-on ac tivation, low-to-high transi- tion at the output of the gate driver only occurs 30 s after the v dd2 power is applied. figure 57. input/output relationship figure 58. timing relationship among desat, fault , and reset figure 59. uvlo for output side v o v in? v in+ normal operation fault condition reset reset v o fault v desat v in? 0 v 5 v 7 v 0 v v in+ blanking time v o v dd2 ? v e 5 v 0 v v uvlo+ v uvlo? v in? v in+
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 27 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g ordering information all packages are lead free per jedec: j-std-020b standard. marking information part number package packing method FOD8318 so 16-pin tube (50 units per tube) FOD8318r2 so 16-pin tape and reel (750 units per reel) FOD8318v so 16-pin, din en/iec 60747-5-5 option tube (50 units per tube) FOD8318r2v so 16-pin, din en/iec 60747-5-5 option tape and reel (750 units per reel) 1 2 8 4 3 5 definitions 1 fairchild logo 2 device number, e.g., ?8318? for FOD8318 3 din en/iec60747-5-5 option (only appears on component ordered with this option) 4 plant code, e.g., ?d? 5 last-digit year code, e.g., ?b? for 2011 6 two-digit work week ranging from ?01? to ?53? 7 lot traceability code 8 package assembly code, j 8318 d x yy kk j v 6 7
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 28 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g reflow profile profile freature pb-free assembly profile temperature minimum (t smin )150c temperature maximum (t smax )200c time (t s ) from (t smin to t smax ) 60?120 seconds ramp-up rate (t l to t p ) 3 c/second max. liquidous temperature (t l )217c time (t l ) maintained above (t l ) 60?150 seconds peak body package temperature 260 c +0 c / ?5 c time (t p ) within 5 c of 260 c 30 seconds ramp-down rate (t p to t l ) 6 c/second max. time 25 c to peak temperature 8 minutes max. time (seconds) temperature (c) time 25 c to peak 260 240 220 200 180 160 140 120 100 80 60 40 20 0 t l t s t l t p t p t smax t smin 120 preheat area max. ramp-up rate = 3 c/s max. ramp-down rate = 6 c/s 240 360
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 29 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g package dimensions package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ notes: unless otherwise specified a) drawing refers to jedec ms-013, variation aa. b) all dimensions are in millimeters. c) dimensions are exclusive of burrs, mold flash and tie bar protrusions d) drawing conforms to asme y14.5m-1994 e) land pattern standard: soic127p1030x275-16n f) drawing file name: mkt-m16frev2
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 30 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g carrier tape specification (soic-16l opto r2 & r2v option) symbol description dimmension in mm w tape width 24.00 0.30 t tape thickness 0.30 0.05 po sprocket hole pitch 4.00 0.10 do sprocket hole diameter 1.50 + 0.10 / -0 d1 pocket hole diameter 1.50 min e sprocket hole location 1.75 0.10 f pocket location 11.50 0.10 p2 2.00 0.10 p pocket pitch 16.00 0.10 ao pocket dimension 11.10 0.10 bo 11.00 0.10 ko 3.20 0.10 k1 2.70 0.10 w1 cover tape width 21.30 0.10 d cover tape thickness 0.05 0.01 max component rotation or tilt 10 t k1 ko d w1 bo ao do po e w f p p2 d1 user direction of feed
?2010 fairchild semiconductor corporation www.fairchildsemi.com FOD8318 rev. 1.1.2 31 FOD8318 ? 2.5 a output current, igbt drive optocoupler with active miller clamp, desaturation dete ction, and isolated fault sensin g

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